This relates generally to integrated circuit packages, and more particularly, to integrated circuit packages with more than one integrated circuit die.
An integrated circuit package typically includes an integrated circuit die and a substrate on which the die is mounted. The die can be coupled to the substrate through bonding wires or solder bumps. Signals from the integrated circuit die may then travel through the bonding wires or solder bumps to the substrate.
As demands on integrated circuit technology continue to outstrip even the gains afforded by ever decreasing device dimensions, more and more applications demand a packaged solution with more integration than possible in one silicon die. In an effort to meet this need, more than one die may be placed within a single integrated circuit package (i.e., a multichip package). As different types of devices cater to different types of applications, more dies may be required in some systems to meet the requirements of high performance applications. Accordingly, to obtain better performance and higher density, an integrated circuit package may include multiple dies arranged laterally along the same plane or may include multiple dies stacked on top of one another.
Emerging trends that would rely on the advantages offered by multichip packages include increasing demands of data centers, the explosion of Internet of Things (IoT), 400G to terabit networking, optical transport, 5G wireless technology, 8K video streaming, etc. These next generation platforms require semiconductor systems that offer higher bandwidth, increased functionality, and increased flexibility while minimizing power consumption and maintaining or reducing its footprint/form factor. These requirements present fairly challenging problems to the system designer.
Conventional multichip packages include multiple dies mounted on an interposer substrate. The use of interposer substrates are, however, oftentimes prohibitively costly to manufacture while also being prone to mechanical issues such as warpage. Interposers sometimes include logic routing fabric for interconnecting the different dies, oftentimes resulting in much longer interconnects, which increases the loading on the driver buffers and limits performance. Moreover, conventional multichip packages that are used in high-speed networking systems (e.g., networking applications that support data transfers of 10 Gbps or more) often have limited flexibility and can only support a single networking protocol.
It is within this context that the embodiments described herein arise.